1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to methods of forming self-aligned contacts on a semiconductor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, there is an constant demand for enhanced functionality of electronic devices which forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules.
However, with some modern devices, operating speed of complex integrated circuits is no longer limited by the switching speed of the individual transistor element, but rather by the electrical performance of the complex wiring system used in such an integrated circuit. Such a wiring system may be formed above the device level and it may include the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level, on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These interconnect structures can be made of a variety of different materials, e.g., copper, and they provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, which connects, on one end, to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors. The opposite end of the vertical contact is conductively coupled to a respective metal line in the metallization layer and/or to a contact region of a further semiconductor based circuit element, in which case the interconnect structure in the contact level is also referred to as local interconnect. The contact structure may comprise contact elements or contact plugs having a generally square or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level have critical dimensions that are on that same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions may be 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy. In some cases, despite a manufacturer's best efforts, there are errors in forming the contact openings in the proper location. When the conductive contacts are formed in these misaligned openings, the performance of the resulting device may be degraded, if not destroyed.
FIG. 1A depicts an illustrative device 100 at the point of fabrication wherein various gate electrode structures 12 have been formed above a semiconductor substrate 10. Each of the illustrative gate electrode structures 12 includes an illustrative gate insulation layer 12A and a sacrificial gate electrode 12B. Also depicted in FIG. 1A are a gate cap layer 14 formed above the sacrificial gate electrode 12B, sidewall spacers 16 positioned proximate the gate electrode 12B, and a liner layer 18. The various structures depicted in FIG. 1A are positioned in a layer of insulating material 20. Also depicted in FIG. 1A are a plurality of metal silicide regions 22 formed in the substrate 10 and a layer of conductive material 24 formed above the device 100 and the metal silicide regions 22. It should be noted that the layer of conductive material 24 is formed above the gate electrode structures 12 at a time when the upper surface 12S of the gate electrode 12B is protected by the gate cap layer 14 and the liner layer 16, which are both typically made of silicon nitride.
Next, using prior art techniques, as shown in FIG. 1B, a CMP (chemical mechanical planarization) process is performed to essentially planarize the various materials positioned above the gate electrode 12B to thereby result in the definition of self-aligned contacts 24C. Unfortunately, in the real world, the planarization process may not result in the nice even planar surface depicted in FIG. 1B. This occurs for a variety of reasons, not the least of which is the fact that this CMP process must typically remove three different types of material, e.g., the layer of conductive material 24, the layer of insulating material 20, the liner layer 16 and the gate layer 14, the latter two being typically comprised of silicon nitride. It is very difficult to perform a CMP process that consistently and reliably planarizes three different types of material layers, e.g., silicon nitride, tungsten and silicon dioxide. Without a substantially uniform and planar surface, additional device fabrication becomes more difficult, especially in areas of photolithography. This is particularly true in modern semiconductor devices as various features now approach the limit of what photolithography tools can directly pattern. Thus, it is vitally important that, to the extent possible, all efforts are made to produce devices that, during intermediate stages of fabrication, do not produce surfaces with excessive topography changes.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.